In recent years, memory employing a resistance varying element has been receiving attention as a candidate for file memory acting as a large capacity data storage medium. As an example of general configuration for aiming large capacity storage employing such a resistance varying memory, there is proposed a method that adopts a cross-point type cell structure where a memory cell is formed at a crossing point of an intersecting bit line and word line.
This cross-point type configuration is characterized in that its configurative elements are generally simple. Moreover, in this cross-point type configuration, miniaturization is easy compared to in a conventional memory cell, storage density of a cell array having memory cells disposed in an array can be increased, and, furthermore, adopting a stacking structure in a longitudinal direction enables memory capacity density to be significantly increased. As a result, this cross-point type configuration has a merit that a degree of integration of a memory cell array can be easily improved.
In such a cross-point type resistance varying memory, in order to achieve a larger capacity, the memory cell array must be made larger. In such a case, it faces some problems such as deterioration in defect rescue efficiency, deterioration in defect rescue replacement, deterioration in operating margin in an memory cell array, and deterioration in operating performance margin due to voltage drop or the like. As a result, there are many problems in achieving a larger capacity simply by a single array configuration.
Accordingly, it has been proposed to divide the memory cell array into a plurality of memory arrays to alleviate these adverse effects. A smallest unit of this divided array is here assumed to be called “a memory mat.” When plural memory mats are present in the memory cell array in this manner, wiring lines linking between the memory mats and a control system circuit for controlling these wiring lines become necessary. At this time, it becomes required to switch connection between local wiring lines in each of the memory mats and global wiring lines distributed through a plurality of the memory mats. There is a problem that circuit area corresponding to a circuit for this kind of switching and to its control circuit increases, leading to an increase in chip area that leads in turn to a reduction in chip yield on the wafer.